gnu make - Makefile which can generate all object files in a specific path -

somewhere going wrong !!

i trying generate object files in ../bin/

but below code generates in corresponding source file directory.

below code, running.

modified code:

lib = $(bin_dir)/libutils.a app = $(bin_dir)/app  cc = gcc ar = ar  cflags = -wall -g ldflags =   all: $(lib) $(app)  src =   $(src_dir)/add.c \         $(src_dir)/sub.c   obj = $(src:.c=.o)   includes = -i$(inc_dir)/ libs = -l../ -l/usr/local/lib -lm  ldflags = -g .suffixes: .c  .c.o:     $(cc) $(includes) -c $(src_dir)/$< -o $(bin_dir)/$@  $(lib): $(obj) $(ar) rcs $(lib) $(obj)  $(bin_dir)/app: $(bin_dir)/test.o \                 $(bin_dir)/t.o \                 $(bin_dir)/libutils.a     $(cc) $(ldflags) -o $@ $^  clean:     rm -f $(lib) $(bin_dir)/* $(src_dir)/*.o *.o 

thank :)

you still have rule:

$(lib): $(obj)     ... 

and obj still src_dir/add.o src_dir/sub.o, that's make try build these objects if object rule works intended. so, first step:

src = $(src_dir)/add.c \ $(src_dir)/sub.c

obj = $(src:.c=.o)
obj = $(patsubst $(src_dir)/%.c,$(bin_dir)/%.o,$(src))

now you'll find object rule,

.c.o:     ... 

doesn't work, because expects find source file in same place object file should go (i.e. $(obj_dir)). replace rule with:

$(bin_dir)/%.o: $(src_dir)/%.c     $(cc) $(includes) -c $< -o $@ 

i notice have no provision building $(bin_dir)/t.o , $(bin_dir)/test.o, app needs them. should that.

further refinements possible, start.