FPGA implement memory mapped register -

i'm relatively new @ fpga (vhdl) programming. have no clue resource cost of different solutions problem... wondering approach makes sense if want implement memory mapped registers inside fpga design. should design 1 address decoder strobes al registers on address match or better design each register own decoder (or @ least each subcomponent pwm generator uses couple of registers in implementation).

thanks in advance insights regards jan

the critical resource not gates (luts), engineering time, , primary concern make design easy manage , modules easy reuse.

for reason alone, should make hierarchical address decode, each module responsible partitioning , decode of address space has been allocated.

so in case, pwm generator should have separate address decoder registers allocated in address space given pwm module @ next higher level in hierarchy.

to learn resource usage can install fpga synthesis tool , experiment different approaches; exercise choose between different implementations.