4-to-1 Multiplexer that implements addition, inversion, AND, OR gates on Verilog -

i started learning verilog semester , got stuck on task create verilog module has uses multiplexed different operations on 2 8-bit inputs. below verilog code wrote, getting several errors not understand. please help!

module eightbit_palu( input[7:0] a, input[7:0] b, input[1:0] sel, output[7:0] f, output ovf );   reg f, ovf;      @ (a , b, sel)      case (sel)         0 : f = + b;             ovf = f[8]^f[7];           1 : f[0] = ~b[0];              f[1] = ~b[1];              f[2] = ~b[2];              f[3] = ~b[3];              f[4] = ~b[4];              f[5] = ~b[5];              f[6] = ~b[6];              f[7] = ~b[7];          2 : f[0] = a[0]&b[0]; f[1] = a[1]&b[1]; f[2] = a[2]&b[2]; f[3] = a[3]&b[3]; f[4] = a[4]&b[4];               f[5] = a[5]&b[5]; f[6] = a[6]&b[6]; f[7] = a[7]&b[7];           3 : f[0] = a[0]|b[0]; f[1] = a[1]|b[1]; f[2] = a[2]|b[2]; f[3] = a[3]|b[3]; f[4] = a[4]|b[4];               f[5] = a[5]|b[5]; f[6] = a[6]|b[6]; f[7] = a[7]|b[7];     endcase  endmodule 

the errors being displayed simulators are:

8: syntax error
10: error: incomprehensible case expression.
11: syntax error
19: error: incomprehensible case expression.
19: syntax error
22: error: incomprehensible case expression.
22: syntax error

two major issues:

first, verilog, series of procedural statements must surrounded begin-end keywords

always @ (*) begin     case (sel)         0 : begin               f = + b;               ovf = f[8]^f[7];              end          1 : begin             f[0] = ~b[0];             ...             end          ...     endcase end 

second, mixing ansi , non-ansi style headers declaring f , ovf wires in portlist, single bit reg inside. pick 1 syntax:

• ansi: (note output reg)

  module eightbit_palu( input[7:0] a, input[7:0] b,    input[1:0] sel, output reg [7:0] f, output reg ovf ); 

• non-ansi:

  module eightbit_palu( a, b, sel, f, ovf );   input[7:0] a;   input[7:0] b;   input[1:0] sel;   output [7:0] f;   output ovf;   reg [7:0] f;   reg ovf;  

---

suggested improvements:

• always @ (a , b, sel) always @*

  • since 2001, verilog supports wild card sensitivity lists combinational logic blocks. helps prevent agents rtl vs synthesized-gates behavioral mismatches, , preferred coding style in verilog. defining sensitivity manually required when strictly following 1995 version of standard.

• you can simplfiy conditions 1, 2, , 3 bitwise operations: (eg. 1 : f = ~b; , 2 : f = & b;, 3 : f = | b;). for-loops options

• ovf inferred latch. latches not necessary bad, need know doing them. recommended use when necessary. what inferred latch , how created when missing else statement in if condition.can explain briefly?